Overview

Features

Master HFDCO oscillator which can be programmed to between 8 MHz and 33.5 MHz with 2 kHz resolution. Free-runs with ± 0.5% accuracy over temperature, or can be locked to the 32.768 kHz crystal oscillator.
A32.768 kHz crystal oscillator with 5-bit programmable padding capacitance giving a frequency adjustment resolution of 4 ppm to allow compensation for crystal variations over temperature. Used for accurate real time clocking and as an accurate frequency source towhich the master HFDCO oscillator can be locked.
2 clock outputs, each of which can be powered independently from VDD or VBAK and can operate either in-phase or in complementary mode. Both are derived from the HFDCO clock with independent postscaling to give frequencies down to 32.768 kHz on CLK0 and 244 Hz on CLK1. When running in battery backup mode, the 32.768 kHz internal system clock can be output on CLK1.
An internal oscillator which is fuse-calibrated to provide a 32.768 kHz clock source as an integrated alternative to the crystal oscillator. Accuracy is better than± 3% over temperature and supply voltage. This oscillator starts immediately on power-up. If an external crystal is present, the crystal oscillator takes over once it has stabilized.
96-bit electrically programmable nonvolatile fuse memory array used for internal calibration and to program various on-chip configuration functions.
7-bit programmable threshold reset comparator which generates a system reset at a selected VDD supply voltage (VBO)between 1.7 V and 4 V with 24 mV resolution. Reset is implemented as active low output.
Programmable reset duration between 6 ms and 5.3 seconds
Less than 10 µA standby current and less than 12 mA maximum operating current (excluding LDO load)
I2C interface with 3-bit fuse-settable address to allow multi-drop capability. Can operate up to 1 MHz. Complies with I2C fast mode specification.
General-purpose 8-bit DAC and comparator used to monitor VDD, VBAK, internal temperature, or an analog input from the SNSE pin. Can be programmed to implement a simple low speed (1 ms) ADC.
General-purpose PWM &PDM output which can be either directly controlled via the I2Cinterface or programmed for use as automatic fan speed control in conjunction with the on-chip temperature measurement
Programmable watchdog counter with a 7.8 ms resolution up to 8 seconds delay
Periodic interrupt timer (PIT) with a 30 µs resolution up to 36 hours
Realtime clock with 1/256 second resolution up to Year 2099 with day,month, year calendar and leap year adjustment; includes RTC alarm
Spread spectrum option on the output clock to offer up to 3% of frequency energy spreading around the programmed center frequency
Battery backup facility, which maintains register contents and RTC operation when VDD collapses. Backup current consumption is less than 2 µA.
1.7 V to 5.5 V operating range on the main VDD supply
0.9 V to 5.5 V operating range on the battery backup supply (VBAK)
Edge-triggered, level-sensitive, and toggling interrupt output (INT)
General-purpose I/O option on the interrupt pin (INT)
Low power, low dropout voltage regulator (LDO) output on PWM pin
Switched mode boost, bootstrap boost, and buck regulation control
56 bytes of control registers including a 9-byte scratchpad
Small 3 mm x 3 mm 16-lead MLP package