Datasheet

Features

• User-Enabled DQPSK Precoder Function
• SFI-5+⁽¹⁾ Compliant FIFO and Deskew functions
• Dual Ground-Referenced High-Speed Single-Ended Output Ports
• 0.3 to 0.7 Volt pp SE Output Level (adjustable for reduced power)
• 11 psec (typical) Rise/Fall Times
• 3.7 psec p-p total jitter (typical)
• Data-to-Data Skew Adjustments for Each Output Data Lane; +/- 0.25UI (Note: 1UI = 1/f_Baud)
• GPPO Connection; 22.5 to 24.5 Gbaud (f_Baud)
• High-Speed Differential Clock Outputs with Highly Stable Clock-Data Skew and Low Phase Noise
• Full (23.5 nominal) and Half-Rate (11.75 GHz nominal) CML Clocks
• Skew control of +/- 0.5UI (Note: 1UI = 1/f_Baud) on Half-Rate Clock
• 0.8 Volt pp Differential Output Level
• BGA launch to hoost printed circuit board
• SONET-compliant Clock Multiplier Unit (CMU) with VCO
• Three User Selectable Reference Clock Input Ports
• Input Reference Clock Rate: 1/4th Client-Side Baud Rate: 703.125 to 765.625 MHz
• Reference Clock Clean-Up Loop Circuitry
• On-Chip PRWS Error Checker and Pattern Generator: 2⁷-1 or 2³¹-1 patterns
• On-Chip Error Counter for Measuring BER
• Lane-by-Lane Error Checking
• SPI Control Interface Supports Wide Range of Logic Families
• 1.2V or 1.8V LVCMOS
• Temperature Sense Output Voltage
• Dual-Power Supply Voltages: +1.2 or +1.8V and -2.8V
• BiCMOS Silicon Germanium Technology for High Reliability and Low-Cost
• Low Power Consumption: 2.4 Watts (typical, HSCLK outputs disabled)

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