Datasheet

Features

• User-Enabled Differential Precoder Function
• SFI-5 Compliant Client-Side Interface (OIF-SFI5-01.02 and OIF-SxI-5-01.0)
• Ground-Referenced High-Speed Differential Output Ports
• 0.5 to 1.0 Volt pp Differential Output Level (Adjustable)
• 9 psec (typical) Rise/Fall Times
• 6 psec p-p Total Jitter (maximum)
• Dual-GPPO Interface
• High-Speed Differential Clock Outputs with Low Phase Noise
• Half-Rate (19.9 to 22.3GHz) and Quarter-Rate (9.95 to 11.15 GHz) User-Enabled Outputs
• Ground-Referenced CML
• Clock-to-Data Skew control of +/- 0.5UI (Note: 1UI = 1/f_Baud) on Half-Rate Clock
• 0.4 to 0.8 Volt pp Differential Output Level (Adjustable)
• BGA Launch to Host Printed Circuit Board
• SONET-compliant Clock Multiplier Unit (CMU) with On-Chip VCO
• Two User Selectable Reference Clock Input Ports
• Input Reference Clock Rate: 1/4th Client-Side Baud Rate: 621.9 to 696.88 MHz
• Reference Clock Clean-Up Loop Circuitry
• PRWS Error Checker and Pattern Generator: 2⁷-1 or 2³¹-1 patterns
• On-Chip Error Counter for Measuring BER
• Lane-by-Lane Error Checking
• 512-Bit Arbitrary Pattern Generator
• SPI Control Interface Supports Wide Range of Logic Families
• 1.2V or 1.8V LVCMOS
• Temperature Sense Output Voltage
• Dual-Power Supply Voltages: +1.2 or +1.8V and -2.8V
• BiCMOS Silicon Germanium Technology for High Reliability and Low-Cost
• Low Power Consumption: 2.4 Watts (typical, HSCLK outputs disabled)

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