ACS8946: Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for OC-12/STM-4 and GbE

The ACS8946 JAM PLL is a Jitter-Attenuating, Multiplying differential Phase-Locked Loop, for generating low jitter output clocks compliant up to SONET OC-12 and STM-4 622.08 MHz specifications. Its primary function is to clean up clock jitter for high performance optical line cards with OC-12 framers and serializers.

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Features

Meets rms jitter requirements of:
- Telcordia GR-253 for OC-3 and OC-12
- ITU-T G.813/G.812 for STM-1 and STM-4 rates
- ETSI EN300-462-7/EN302-084 up to STM-16 rates
PLL bandwidth and jitter peaking fully adjustable—supports PLL loop bandwidths from 2 kHz for superior input jitter filtering
Typical jitter generation down to:
- 0.3 ps rms for 250 kHz to 5 MHz band for G.813, or EN300 462, at STM-4 (OC-12) rates
- 2.8 ps rms for 12 kHz to 20 MHz band (against 4.02 ps rms for GR-253-CORE at OC-48 rate)

ITU, ETSI and Telcordia frequency band results shows exceptional performance in a “Real World” environment (low PLL bandwidth of 2 KHz and a typical input from an ACS8525 partner IC):
- 0.4 ps rms for 250 kHz to 5 MHz band for G.813, or EN300 462, at STM-4 (OC-12) rates
- 2.8 ps rms for 12 kHz to 20 MHz band
Tracking range ±400 ppm about a wide range of input frequencies
Manual or automatic control of reference selection
External feedback option
LOS alarms for each input, and for selected reference
3.3 V operation, - 40 to +85°C temperature range
Small outline leadless 7 mm x 7 mm QFN48 package
Lead (Pb)-free version available (ACS8946T), RoHS and WEEE compliant